1. Field of the Invention
The present invention relates to a monitor circuit for monitoring administration information of a frame received during high-speed data communication.
2. Description of the Related Art
SDH (Synchronous Digital Hierarchy) is one of world standards for optical transmission network for realizing high-speed data communication. The SDH has a synchronous transfer mode called an STM (Synchronous Transfer Module) as data multiplexing unit. The bit rate of STM-1 (Synchronous Transfer Module Level One) which is the base of the STEM is 155.52 Mb/s.
The frame of the STM is constituted by a two-dimensional byte array composed of 9 rowsxc3x97270 columns. A portion of 9 rowsxc3x979 columns in head is called a section overhead (hereinafter called an xe2x80x9cSOHxe2x80x9d). A next portion composed of 9 rowsxc3x97261 columns is called a payload. The SOH is an administration portion having a frame synchronous signal and maintenance information added to the payload. Actual data, which has been multiplexed, is accommodated in the payload.
Since one frame of the STM is transferred at 125 micro-seconds, the bit rate varies according to the number of bytes for data concerning 1 rowxc3x971 column. Since data in 1 rowxc3x971 column is 1 byte data in STM-1, the bit rate is 155.52Mb/s because 9 rowsxc3x97270 bytesxc3x97(1/125 microseconds) =155.52 Mb/s. The SDH has several standards including, for example, STM-4 having a bit rate which is four times the bit rate of STM-1 such that data of 1 rowxc3x971 column is four bytes, STM-16 having a bit rate which is 16 times the foregoing bit rate such that data of 1 rowxc3x971 column is 16 bytes and STM-64 having a bit rate which is 64 times the foregoing bit rate such that data of 1 rowxc3x971 column is 64 bytes.
The structure of the hardware for performing data communication by the SDH with which transfer and receipt concerning one frame are performed at high speed requires a high-speed RAM (Random Access Memory) adaptable to the high-speed operation or a plurality of low-speed RAM units. That is, when a low-speed RAM is employed, the operation speed of the low-speed RAM is a bottleneck. Therefore, a high-speed RAM has to be substituted for the low-speed RAM or a changeover structure must be employed in which a plurality of low-speed RAM units are provided. Since the bit rate of, for example, STM-64, is 64 times the bit rate of STM-1, a RAM having a capacity which is 64 times the bit rate of STM-1 is required. However, there arises a problem that the high-speed RAM is a costly unit and a satisfactorily large capacity cannot be realized. Another problem arises in that the low-speed RAM having a sufficiently large capacity and, however, incorporating a large number of signal lines encounters a fact that the circuit becomes too complicated and enlarged excessively.
An object of the present invention is to provide a low-cost and small-size monitor circuit which is used in a receiving apparatus for receiving test data of high-speed data communication and which monitors administration information of a received frame.
A testing apparatus in which pseudo data is transferred or received is generally used to evaluate the data communication. Also data communication using the SDH is arranged similarly. That is, the frame is structured such that valid administration data is stored in only the SOH. Moreover, pseudo data is stored in the payload. Thus, data communication which is performed by the SDH can be tested.
Therefore, if the testing apparatus for testing data communication is arranged such that the receiver unit is able to validly evaluate only administration data of the SOH, a required function can be realized. In the foregoing case, a necessity for structuring the receiver unit to be the same as the actual receiver unit for receiving SDH communication data can be eliminated.
According to a first aspect of the present invention, there is provided a monitor circuit for extracting administration information of a received communication frame, the monitor circuit comprising:
a storage circuit for storing administration information; and
a change-over switch for receiving the communication frame and performing change-over to output administration information to the storage circuit only when administration information of the communication frame is received in response to a predetermined input signal.
In the first aspect of the present invention, the monitor circuit is structured such that the storage circuit stores administration information and the change-over switch receives the communication frame to output administration information to the storage circuit only when administration information of the communication frame is received in response to the predetermined input signal.
Therefore, in the first aspect of the present invention, the administration information of the received communication frame can be extracted easily. Thus, the circuit can be simplified. Moreover, the size of the storage circuit for storing administration information can be reduced. Therefore, a small-size monitor circuit can be provided. Although the storage circuit required when high-speed data communication is performed is a costly circuit, the cost of the monitor circuit can be reduced because only a minimum storage capacity is required.
According to a second aspect of the present invention, there is provided a monitor circuit according to the first aspect of the present invention, wherein
the communication frame is constituted by a plurality of administration information items and communication data,
the storage circuit incorporates:
a high-speed storage circuit which temporarily stores an administration information item among the plural administration information items which is input from the change-over switch and which is capable of performing a storing process at high speed and
a low-speed storage circuit which receives the administration information temporarily stored in the high-speed storage circuit, which stores all of the plural administration information items and which is capable off performing a storing process at low speed, and
the change-over switch is structured to perform changeover between output of the communication frame to the high-speed storage circuit and output from the high-speed storage circuit to the low-speed storage circuit such that when the change-over switch receives an administration information item of the communication frame, the change-over switch outputs the administration information item to the high-speed storage circuit and when the change-over switch receives one communication data item of the communication frame, the change-over switch outputs the administration information item stored in the high-speed storage circuit to the low-speed storage circuit so that all of the plural administration Information items of the communication frame are stored and extracted into low-speed storage circuit.
According to the second aspect of the present invention, there is provided a monitor circuit according to the first aspect of the present invention, wherein the communication frame is constituted by a plurality of administration information items and communication data. The storage circuit incorporates the high-speed storage circuit and the low-speed storage circuit. The high-speed storage circuit, at high speed, temporarily stores an administration information item among the plural administration information items which is input from the change-over switch. The low-speed storage circuit receives the administration information Item temporarily stored in the high-speed storage circuit and, at low speed, stores all of the plural administration information items. The change-over switch is structured to perform changeover between output of the communication frame to the high-speed storage circuit and output from the high-speed storage circuit to the low-speed storage circuit. Thus, switching is performed such that when an administration information item in the communication frame is received, the administration information item is output to the high-speed storage circuit. When a communication data in the communication frame is received, the administration information item stored in the high-speed storage circuit is output to the low-speed storage circuit. Thus, all of the plural administration information items in the communication frame are stored and extracted into the low-speed storage circuit.
In the second aspect of the present invention, the monitor circuit is structured such that the high-speed storage circuit is simply required to temporarily store one administration information if the communication frame is composed of a plurality of administration information items and communication data. Therefore, only a minimum storage capacity is required for the high-speed storage circuit. Hence it follows that a low-cost monitor circuit can be realized. Since the low-speed storage circuit is simply required to receive and store administration information temporarily stored in the high-speed storage circuit, the circuit structure can be simplified. As a result, a small-size monitor circuit can be provided.
According to a third aspect of the present invention, there is provided a monitor circuit according to the second aspect of the present invention, wherein the communication frame is for use in SDH.
The third aspect of the present invention permits the monitor circuit to be applied to the SDH standardized as high speed data communication. Therefore, a monitor circuit which is satisfactory from a viewpoint of practical use can be provided.
According to a fourth aspect of the present invention, there is provide a monitor circuit according to the second or third aspect of the present invention, wherein the predetermined input signal is an identification signal for identifying a period in which the administration information item of the communication frame is input and a period in which the communication data item is input.
In the fourth aspect of the present invention, the monitor circuit is structured such that the predetermined input signal is the identification signal for identifying two data items. Therefore, the foregoing signal can easily be realized by using only two signal levels which are, for example, a high level and a low level. Therefore, the structure of the circuit can be simplified and the size of the monitor circuit can be reduced.
According to a fifth aspect of the present invention, there is provided a monitor circuit comprising a counter for receiving the predetermined input signal and counting the number of input times of the administration information items until a predetermined number of times at which all of the plural administration information items of the communication frame are stored and extracted into the low-speed storage circuit, wherein
when the counter has counted the predetermined number of times, all of the plural administration information items of the communication frame stored in the low-speed storage circuit are output.
According to the fifth aspect of the present invention, there is provided the monitor circuit according to the fourth aspect, wherein the counter receives the predetermined input signal and counts the number of input times of the administration information items until a predetermined number of times at which all of the plural administration information items of the communication frame are stored and extracted into the low-speed storage circuit, wherein when the counter has counted the predetermined number of times, all of the plural administration information items of the communication frame stored in the low-speed storage circuit are output.
In the fifth aspect of the present invention, there has the structure that all of the plural administration information items in the communication frame have been stored in the low-speed storage circuit. Then, the administration information items are automatically output from the low-speed storage circuit. Therefore, a monitor circuit which is satisfactory from a viewpoint of practical use can be provided.